Reporting pcie device error information

ABSTRACT

An information handling system includes multiple PCIe devices and a basic input/output system (BIOS). The BIOS receive a system management interrupt (SMI). The SMI is in response to a detection of an error on a first PCIe device of the PCIe devices. The BIOS collect data associated with the first PCIe device. The data includes a friendly full device description for the first PCIe device. Based on the friendly full device description, the BIOS determine a friendly name for the PCIe device. The BIOS provide an error message on a display device of the information handling system. The error message includes a type of the error detected and the friendly name for the PCIe device.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, andmore particularly relates to reporting PCIe device error information inan information handling system.

BACKGROUND

As the value and use of information continues to increase, individualsand businesses seek additional ways to process and store information.One option is an information handling system. An information handlingsystem generally processes, compiles, stores, and/or communicatesinformation or data for business, personal, or other purposes. Becausetechnology and information handling needs and requirements may varybetween different applications, information handling systems may alsovary regarding what information is handled, how the information ishandled, how much information is processed, stored, or communicated, andhow quickly and efficiently the information may be processed, stored, orcommunicated. The variations in information handling systems allow forinformation handling systems to be general or configured for a specificuser or specific use such as financial transaction processing,reservations, enterprise data storage, or global communications. Inaddition, information handling systems may include a variety of hardwareand software resources that may be configured to process, store, andcommunicate information and may include one or more computer systems,data storage systems, and networking systems.

SUMMARY

An information handling system includes multiple PCIe devices and abasic input/output system (BIOS). The BIOS may receive a systemmanagement interrupt (SMI). The BIOS may collect data associated withthe first PCIe device. The data includes a peripheral componentinterconnect express (PCIe) location with segment, bus, device,function. Based on the information, the BIOS may get a friendly name forthe PCIe device. The BIOS may provide an error message on a displaydevice of the information handling system. The error message may includea type of the error detected and the friendly name for the PCIe device.

BRIEF DESCRIPTION OF THE DRAWINGS

It will be appreciated that for simplicity and clarity of illustration,elements illustrated in the Figures have not necessarily been drawn toscale. For example, the dimensions of some of the elements areexaggerated relative to other elements. Embodiments incorporatingteachings of the present disclosure are shown and described with respectto the drawings presented herein, in which:

FIG. 1 is block diagram of a portion of an information handling systemaccording to at least one embodiment of the disclosure;

FIGS. 2 and 3 are block diagram of examples of aspects of an unifiedextensible firmware interface (UEFI) environment according to a specificembodiment of the present disclosure;

FIG. 4 illustrates a block diagram of portions an information handlingsystem in a boot mode and a runtime mode according to an embodiment ofthe present disclosure;

FIG. 5 illustrates a method for reporting PCIe device error informationin an information handling system according to an embodiment of thepresent disclosure; and

FIG. 6 is a block diagram of a general information handling systemaccording to an embodiment of the present disclosure.

The use of the same reference symbols in different drawings indicatessimilar or identical items.

DETAILED DESCRIPTION OF DRAWINGS

The following description in combination with the Figures is provided toassist in understanding the teachings disclosed herein. The followingdiscussion will focus on specific implementations and embodiments of theteachings. This focus is provided to assist in describing the teachings,and should not be interpreted as a limitation on the scope orapplicability of the teachings. However, other teachings can certainlybe used in this application. The teachings can also be used in otherapplications, and with several different types of architectures, such asdistributed computing architectures, client/server architectures, ormiddleware server architectures and associated resources.

FIG. 1 shows an information handling system 100 including centralprocessing unit (CPU) 102. For purposes of this disclosure, aninformation handling system may include any instrumentality or aggregateof instrumentalities operable to compute, classify, process, transmit,receive, retrieve, originate, switch, store, display, manifest, detect,record, reproduce, handle, or utilize any form of information,intelligence, or data for business, scientific, control, entertainment,or other purposes. For example, an information handling system may be apersonal computer, a PDA, a consumer electronic device, a network serveror storage device, a switch router or other network communicationdevice, or any other suitable device and may vary in size, shape,performance, functionality, and price. The information handling systemmay include memory, one or more processing resources such as a centralprocessing unit (CPU) or hardware or software control logic. Additionalcomponents of the information handling system may include one or morestorage devices, one or more communications ports for communicating withexternal devices as well as various other I/O devices, such as akeyboard, a mouse, and a video display. The information handling systemmay also include one or more busses operable to transmit communicationsbetween the various hardware components.

Information handling system 100 includes CPU 102 6. In an example, theinformation handling system 100 can be a server, a personal computer, alaptop computer, or the like. PCIe devices may include, but are notlimited to, dual in-line memory modules (DIMMs), embedded serialadvanced technology attachment (SATA) devices, redundant array ofindependent disks (RAID) controllers, NICs, PCIe solid-state drives(SSDs), and integrated network interface cards (NICs). CPU 102 includesmultiple peripheral component interconnect express (PCIe) root ports 104and 106, a processor core 110, a basic input/output system (BIOS) 112,an operating system (OS) 114, a system management mode (SMM) memory 116,and a memory controller 118. BIOS 112 includes a system managementinterrupt (SMI) handler 120 and a SMM reliability, availability, andserviceability (RAS) error handler 122, both of which in turn may befirmware processes executed by CPU 102. In an example, processor 110 mayperform one or more operations via OS 114. In an example, informationhandling system 100 and CPU 102 may each include additional componentswithout varying from the scope of this disclosure. For example, CPU 102may be a multicore CPU, such that the CPU may include more processorcores than just processor core 110, and more memory controllers. In thisexample, each processor core may have one or more DIMMs assigned to theprocessor core. However, for brevity and clarity the description of FIG.1 will be described with respect to processor core 110 and PCIe devicesassociated with PCIe root ports 104 and 106.

Processor core 110 can operate to provide data and control interfaces toone or more PCIe devices, such as DIMMs in accordance with a particularmemory architecture. For example, processor core 110 and the off-packageDIMMs may operate in accordance with a Double-Data Rate (DDR) standard,such as a JEDEC DDR4 or DDR5 standard. Memory 116 may be any suitabletype of memory including, but not limited to, a system management randomaccess memory (SMRAM) located internally on the processor packageitself. In an example, SMRAM may include dedicated code, such as SMIhandling code, SMM RAS error handling code, and data defined a buildtime. In this example, the SMI handling code may enable CPU 102 toappropriately respond to each individual SMI source. Memory 116 may alsostore a look-up table 130.

Referring now to FIG. 2 , examples of aspects of an EFI environmentcreated by BIOS/EFI firmware 140 of the information handling system aredescribed. For example, BIOS/EFI firmware 140 includes firmwarecompatible with the EFI specification. The EFI specification describesan interface between OS 202 and BIOS/EFI firmware 140. Particularly, theEFI specification defines the interface that BIOS/EFI firmware 140implements and the interface that OS 202 may use in booting. Accordingto an implementation of EFI, both EFI and legacy BIOS support modulesmay be present in BIOS/EFI firmware 140. This allows the informationhandling system to support both firmware interfaces. Addition detailsregarding the architecture and operation of the EFI are provided below.

FIG. 3 shows a block diagram of a software architecture 300 thatillustrates aspects of UEFI 140 of FIG. 1 and OS 202 of FIG. 2 .Specifically, software architecture 300 includes platform hardware 312and OS 202. Platform specific firmware 308 may retrieve OS program codefrom UEFI system partition 314 using OS loader 302, also known as a bootloader or OS boot loader. OS loader 302 may retrieve OS program codefrom other locations, including from attached peripherals or fromfirmware 140, itself. An OS partition 316 may also be present. Oncestarted, OS loader 302 continues to boot OS 202. OS loader 302 may useUEFI boot services 304 to support other specifications 318. Examples ofother supported specifications 318 include advanced configuration andpower management interface (ACPI), system management BIOS (SMBIOS), andthe like. UEFI boot services 304 may provide interfaces for devices andsystem functionality that can be used during boot time. UEFI runtimeservices 306 may be available to OS loader 302 during the boot phase andto OS 202 when running. For example, runtime services 306 may be presentto ensure appropriate abstraction of base platform hardware resourcesthat may be needed by OS 202 during normal operation.

UEFI allows extension of platform firmware by loading UEFI drivers andUEFI application images which, when loaded, have access to UEFI runtimeand boot services 304. Various program modules provide the boot andruntime services. These program modules may be loaded by boot loader 310at system boot time. EFI boot loader 310 is a component in the UEFIfirmware that determines which program modules should be explicitlyloaded and when. Once the UEFI firmware is initialized, it passescontrol to boot loader 310. Boot loader 310 may be then responsible fordetermining which program modules to load and in which order.

UEFI images can include UEFI drivers, applications, and boot loaders,and are a class of files defined by UEFI that contain executable code.UEFI boot loader 310 and a boot manager in particular, is a firmwarepolicy engine that is in charge of loading the operating system loaderand all necessary drivers. UEFI applications can be loaded by the bootmanager or by other UEFI applications to accomplish platform specifictasks within the boot services environment. A UEFI driver is a module ofcode typically inserted into firmware via protocols interfaces. UEFIdrivers can be loaded by the boot manager, firmware conforming to theUEFI specification, or by other UEFI applications. Each UEFI imageincludes one or more UEFI protocols. A UEFI protocol, also referred toas a protocol interface, is much like a class in object-orientedprogramming, providing an interface structure containing datadefinitions, and a set of functions, such as functions to access adevice. Each UEFI protocol includes a globally unique identifier (GUID),which is a 128-bit value used to differentiate services and structuresin the boot services environment.

The UEFI boot flow can be divided into a sequence of phases, including apre-EFI initialization (PEI) phase, followed by a driver executionenvironment (DXE) phase, a boot device selection (BDS) phase, and a runtime (RT) phase. The UEFI boot sequence can include additional phases,and one or more phases can be subdivided into two or more sub-phases.For clarity and brevity, details of these phases will not be describedexcept to describe aspects of the present disclosure. The DXE phase iswhere most of the system initialization is performed. Pre-EFIInitialization (PEI), the phase prior to DXE, is responsible forinitializing permanent memory in the platform so that the DXE phase canbe loaded and executed. There are several components in the DXE phase,including a DXE foundation, DXE dispatcher, and a set of DXE drivers.

Referring back to FIG. 1 , during runtime of information handling system100 one or more components, such as processor core 110, may monitor forerrors in PCIe devices in communication with PCIe root ports 104 and106. In certain examples, these errors may be PCIe correctable errors,PCIe uncorrectable non-fatal errors, PCIe uncorrectable fatal errors, orthe like. If a detected error is a PCIe error, processor core 110 mayprovide a SMI to SMI handler 120 of BIOS 112 firmware. In response tothe SMI, SMI handler 120 may cause CPU 102 to enter a SMM. While in theSMM, CPU 102 may execute SWIM RAS error handler 122 to collect and loginformation associated with the PCIe error. For example, BIOS 112 mayretrieve the available data or information for a PCIe device that hadthe PCIe error.

In previous information handling systems, the BIOS would collect alocation for the PCIe device associated with the PCIe error in a PCIeslot. In the previous information handling systems, the locationinformation would vary based on the type of device experiencing theerror. For example, the BIOS would collect a physical slot number in abitfield for PCIe adaptors. For other PCIe devices, such as embeddeddevices, slimline (SL) devices, or the like, users of the previousinformation handling systems would be provided with a PCIe for theaffected device. For example, if a PCIe error, such as a PCI1360 fatalerror, occurred for an RAID controller in slot 1 of a previousinformation handling system, the BIOS would provide the user with anexemplary message stating “A fatal error was detected on slot 1”. Inanother example, if a PCIe error, such as a PCI1360 fatal error,occurred for an integrated NIC of a previous information handlingsystem, the BIOS would provide the user with an exemplary messagestating “A fatal error was detected on Bus 0x21, Device 0x0, Function0”.

Information handling system 100 may be improved by BIOS 112 creating,and storing in SMM memory 116, a lookup table 140 linking or correlatinga friendly full device description for each device to a respective userfriendly name for the same device. Based on the lookup table, BIOS 112may provide the user friendly name to the user, such that device may beeasily identified. Using the two examples above, if an uncorrectablefatal error PCI1360 occurred for an RAID controller in slot 1, SMM RASerror handler 122 of BIOS 112 may provide the user with an exemplarymessage stating “A fatal PCIe error was detected on the RAID controllerin slot 1 (Segment 0x00, Bus 0x21, Device 0x0, Function 0)”. If anuncorrectable fatal error PCI1360 occurred for an integrated MC, SMM RASerror handler 122 of BIOS 112 may provide the user with an exemplarymessage stating “A fatal error was detected on the Integrated NIC 1 Port2 Partition 3 (Segment 0x00, Bus 0x21, Device 0x0, Function 0)”. Incertain examples, the components within information handling system 100may perform any suitable operations to provide or report PCIe deviceerror information that may be easily understood by a user, as will bedescribed herein.

During the PEI phase of the boot process, BIOS 112 may collectinformation associated with all PCI devices, such as PCIe devices incommunication with PCIe root ports 104 and 106, in information handlingsystem 100. In an example, the collection of the information for thedevices may be performed during a PCIe enumeration process forinformation handling system 100. In this example, BIOS 112 may executethe enumeration process during the DXE phase of the boot process. Incertain examples, the PCIe enumeration process may include determiningmemory requirements and configuring the PCIe devices.

After PCIe enumeration process is complete, BIOS 112 may generatelook-up table 140. In an example, look-up table 140 may include theclass of the PCIe devices, PCI addresses (Segment/Bus/Device/Function)for the devices, friendly full device description, friendly devicenames, or the like. In certain examples, the friendly name may be anysuitable alphanumeric string to enable a user to quickly identify thedevice. In an example, BMC RAS handler may retrieve the friendly namefrom lookup table 140 by matching the PCI address(Segment/Bus/Device/Function) of the PCIe device reporting the error inthe lookup table. An exemplary look-up table 140 showing a devicefriendly full device description and friendly name is provide below asTable 1:

TABLE 1 Friendly Full Device Description Friendly Name DIMM.Socket.A1DIMM A1 RAID.Slot.1 RAID Controller in Slot 1 RAID.Integrated.1Integrated RAID Controller 1 NIC.Slot.3-2-1 NIC in Slot 3, Port 2,Partition 1 Disk.SATAEmbedded.A Disk on Embedded SATA Port A

As illustrated in Table 1 above, the friendly name for a device may beprovided to a user to provide more information associated with thedevice. For example, a user may eventually identify the PCIe device inrow 6 of Table 1 based on the friendly full device description, Disk.SATAEmbedded.A. However, the friendly name, Disk on Embedded SATA PortA, for the PCIe device provides a clearer description to enable the userto quickly identify both the device type and location for thecorresponding PCIe device.

Referring to FIG. 4 , information handling system 100 may be in a PCII/O ready phase 402 of the DXE phase, and a runtime 404. Operations ofinformation handling system 100 will be described with respect to FIGS.1 and 4 .

During the PCI I/O ready phase 402 of the DXE phase, BIOS 112 mayprovide look-up table 140 to SMM error handler 122 at operation 410. Inan example, look-up table 140 may be provided in any suitable manner.For example, BIOS 112 may store look-up table 140 in SMM memory 116 andprovide a pointer for the memory location to the SMM RAS driver of SMMRAS error handler 122. After look-up table 140 is provided to the SMMRAS driver and the boot operations are completed, BIOS 112 may pass theoperation of information handling system 100 to runtime operations bybooting information handling system 100 at operation 412.

During runtime 404 of information handling system 100, one or morecomponents, such as processor core 110 executing OS 122, may monitor forerrors in PCIe devices in communication with PCIe root ports 104 and106. In certain examples, these errors may be PCIe correctable errors,PCIe uncorrectable non-fatal errors, PCIe uncorrectable fatal errors, orthe like. If a detected error is a PCIe error, processor core 110 mayprovide a SMI to SMI handler 120 of BIOS 112 firmware. In response tothe SMI, SMI handler 120 may cause CPU 102 to enter a SMM. While in theSMM, CPU 102 may execute SMM RAS error handler 122 to collect and loginformation associated with the PCIe error. For example, BIOS 112 mayretrieve the available data or information for a PCIe device that hadthe PCIe error.

In an example, the data or information for the PCIe device may includethe PCIe address and friendly full device description associated withthe PCIe device. Based on the collected or retrieved information, SMMRAS error handler 122 may correlate this information with a friendlydevice name the PCIe device. In an example, SMM RAS error handler 122may perform the correlation between the friendly full device descriptionand the friendly device name based on look-up table 140. In response todetermining or retrieving the friendly device name, SMM RAS errorhandler 120 may provide error information and the friendly device nameto a user of information handling system 100. In an example, SMM RASerror handler 122 may provide the error information and the friendlydevice name on a graphical user interface (GUI) 414 of a display device,such as display 634 of FIG. 6 . An exemplary error message 414 may be“PCIe uncorrectable error on VOSS PCIe SSD in Slot 11”. In certainexamples, other exemplary error messages 414 may include “Criticalmemory event detected on DIMM A1” or “A fatal PCIe error was detected onthe PCIe SSD in Slot 2 in Bay 1 (Segment Bus 0x21, Device 0x0, Function0)”.

FIG. 5 illustrates a method 500 for reporting PCIe device errorinformation according to an embodiment of the present disclosure,starting at block 502. In an example, the method 500 may be performed byany suitable component including, but not limited to, BIOS 112 of FIG. 1. It will be readily appreciated that not every method step set forth inthis flow diagram is always necessary, and that certain steps of themethods may be combined, performed simultaneously, in a different order,or perhaps omitted, without varying from the scope of the disclosure.

At block 504, a BIOS power-on self test (POST) is begun. At block 506, aPCIe enumeration process is performed for the PCIe devices in theinformation handling system. In certain examples, the PCIe enumerationprocess may include determining memory requirements and configuring thePCIe devices. At block 508, information for all PCI devices in aninformation handling system is collected. In an example, the informationfor the PCI devices is collected during an early stage of the BIOS POST,such as during the PEI phase of boot process.

After PCIe enumeration process is complete, a look-up table is generatedat block 510. In an example, a BIOS of the information handling systemmay generate the look-up table. In certain examples, the look-up tablemay include the class of the PCIe devices, PCI addresses(Segment/Bus/Device/Function) for the devices, friendly names or uniqueidentification strings of devices, or the like. At block 512, thelook-up table is copied to a SMM RAS driver. In an example, the look-uptable may be copied during the DXE phase of the boot process, and may becopied from a DXE RAS driver to SMM RAS driver. In certain examples, theSWIM RAS driver may be utilized by a BIOS based on a SMI received duringruntime operations of the information handling system. In an example,the DXE RAS driver may create the look-up table may be created duringPOST, and utilize a memory that may be de-allocated or released forother usage at the end of POST. In this example, the data of the look-uptable may be coped to a persistent SWIM memory (SMRAM) for use in OSruntime so that the look-up table data will not be lost.

At block 514, the BIOS POST is completed, and runtime operations of theinformation handling system as executed. At block 516, a PCIe error isdetected during the runtime. In an example, the PCIe error may be PCIecorrectable errors, PCIe uncorrectable non-fatal errors, or PCIeuncorrectable fatal errors. At block 518, a PCIe address associated withthe PCIe error is correlated with a friendly device name or uniqueidentification string for the PCIe device at the PCIe address. In anexample, the correlation between the PCIe address for the error with theunique device identification string may be performed by the SMM RASerror handler utilizing the look-up table. At block 520, the PCIe errorinformation is provide to a user of the information handling system, andthe flow ends at block 522. In an example, the PCIe error informationmay include a description of the error, the address of the error, andthe friendly name or unique device identification string for the PCIedevice, or the like. In certain examples, the PCIe error information maybe provided via a GUI on a display device associated with theinformation handling system.

FIG. 6 shows a generalized embodiment of an information handling system600 according to an embodiment of the present disclosure. Informationhandling system 600 can include devices or modules that embody one ormore of the devices or modules described below and operates to performone or more of the methods described below. Information handling system600 includes a processors 602 and 604, an input/output (I/O) interface610, one or more PCIe root ports, memories 620 and 625, a graphicsinterface 630, a basic input and output system/universal extensiblefirmware interface (BIOS/UEFI) module 640, a disk controller 650, aserial-attached small computer system interface (SCSI) solid state (SAS)drive 651, a serial Advanced Technology Attachment (SATA) drive 653, aSATA drive 654, a PCIe solid state drive (SSD) 655, an optical diskdrive (ODD) 656, an I/O bridge 670, one or more add-on resources 674, atrusted platform module (TPM) 676, a network interface 680, a managementdevice 690, and a power supply 695. Processors 602 and 604, I/Ointerface 610, memory 620, graphics interface 630, BIOS/UEFI module 640,disk controller 650, SAS 651, SATA 653, SATA 654, PCIe SSD 655, ODD 656,I/O bridge 670, add-on resources 674, TPM 676, and network interface 680operate together to provide a host environment of information handlingsystem 600 that operates to provide the data processing functionality ofthe information handling system. The host environment operates toexecute machine-executable code, including platform BIOS/UEFI code,device firmware, operating system code, applications, programs, and thelike, to perform the data processing tasks associated with informationhandling system 600.

In the host environment, processor 602 is connected to I/O interface 610via processor interface 606, and processor 604 is connected to the I/Ointerface via processor interface 608. Memory 620 is connected toprocessor 602 via a memory interface 622. Memory 625 is connected toprocessor 604 via a memory interface 627. Graphics interface 630 isconnected to I/O interface 610 via a graphics interface 632 and providesa video display output 636 to a video display 634. In a particularembodiment, information handling system 600 includes separate memoriesthat are dedicated to each of processors 602 and 604 via separate memoryinterfaces. An example of memories 620 and 625 include random accessmemory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatileRAM (NV-RAM), or the like, read only memory (ROM), another type ofmemory, or a combination thereof.

BIOS/UEFI module 640, disk controller 650, and I/O bridge 670 areconnected to I/O interface 610 and PCIe root ports 611 via an I/Ochannel 612. An example of I/O channel 612 includes a PeripheralComponent Interconnect (PCI) interface, a PCI-Extended (PCI-X)interface, a high-speed PCI-Express (PCIe) interface, another industrystandard or proprietary communication interface, or a combinationthereof. I/O interface 610 can also include one or more other I/Ointerfaces, including an Industry Standard Architecture (ISA) interface,a Small Computer Serial Interface (SCSI) interface, an Inter-IntegratedCircuit (I²C) interface, a System Packet Interface (SPI), a UniversalSerial Bus (USB), another interface, or a combination thereof. BIOS/UEFImodule 640 includes BIOS/UEFI code operable to detect resources withininformation handling system 600, to provide drivers for the resources,initialize the resources, and access the resources. BIOS/UEFI module 640includes code that operates to detect resources within informationhandling system 600, to provide drivers for the resources, to initializethe resources, and to access the resources.

PCIe root port 611 may connect with RAID controller 613, which in turnconnects the PCIe root port to SATA 653 and to PCIe SSD 655. Diskcontroller 650 includes a disk interface 652 that connects the diskcontroller to SAS 651, to SATA 654, to ODD 656, and to disk emulator650. An example of disk interface 652 includes an Integrated DriveElectronics (IDE) interface, an Advanced Technology Attachment (ATA)such as a parallel ATA (PATA) interface or a serial ATA (SATA)interface, a SCSI interface, a USB interface, a proprietary interface,or a combination thereof.

I/O bridge 670 includes a peripheral interface 672 that connects the I/Obridge to add-on resource 674, to TPM 676, and to network interface 680.Peripheral interface 672 can be the same type of interface as I/Ochannel 612 or can be a different type of interface. As such, I/O bridge670 extends the capacity of I/O channel 612 when peripheral interface672 and the I/O channel are of the same type, and the I/O bridgetranslates information from a format suitable to the I/O channel to aformat suitable to the peripheral channel 672 when they are of adifferent type. Add-on resource 674 can include a data storage system,an additional graphics interface, a network interface card (NIC), asound/video processing card, another add-on resource, or a combinationthereof. Add-on resource 674 can be on a main circuit board, on separatecircuit board or add-in card disposed within information handling system600, a device that is external to the information handling system, or acombination thereof.

Network interface 680 represents a NIC disposed within informationhandling system 600, on a main circuit board of the information handlingsystem, integrated onto another component such as I/O interface 610, inanother suitable location, or a combination thereof. Network interfacedevice 680 includes network channels 682 and 684 that provide interfacesto devices that are external to information handling system 600. In aparticular embodiment, network channels 682 and 684 are of a differenttype than peripheral channel 672 and network interface 680 translatesinformation from a format suitable to the peripheral channel to a formatsuitable to external devices. An example of network channels 682 and 684includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernetchannels, proprietary channel architectures, or a combination thereof.Network channels 682 and 684 can be connected to external networkresources (not illustrated). The network resource can include anotherinformation handling system, a data storage system, another network, agrid management system, another suitable resource, or a combinationthereof.

Management device 690 represents one or more processing devices, such asa dedicated baseboard management controller (BMC) System-on-a-Chip (SoC)device, one or more associated memory devices, one or more networkinterface devices, a complex programmable logic device (CPLD), and thelike, which operate together to provide the management environment forinformation handling system 600. In particular, management device 690 isconnected to various components of the host environment via variousinternal communication interfaces, such as a Low Pin Count (LPC)interface, an Inter-Integrated-Circuit (I2C) interface, a PCIeinterface, or the like, to provide an out-of-band (00B) mechanism toretrieve information related to the operation of the host environment,to provide BIOS/UEFI or system firmware updates, to managenon-processing components of information handling system 600, such assystem cooling fans and power supplies. Management device 690 caninclude a network connection to an external management system, and themanagement device can communicate with the management system to reportstatus information for information handling system 600, to receiveBIOS/UEFI or system firmware updates, or to perform other task formanaging and controlling the operation of information handling system600.

Management device 690 can operate off of a separate power plane from thecomponents of the host environment so that the management devicereceives power to manage information handling system 600 when theinformation handling system is otherwise shut down. An example ofmanagement device 690 include a commercially available BMC product orother device that operates in accordance with an Intelligent PlatformManagement Initiative (IPMI) specification, a Web Services Management(WSMan) interface, a Redfish Application Programming Interface (API),another Distributed Management Task Force (DMTF), or other managementstandard, and can include an Integrated Dell Remote Access Controller(iDRAC), an Embedded Controller (EC), or the like. Management device 690may further include associated memory devices, logic devices, securitydevices, or the like, as needed or desired.

Although only a few exemplary embodiments have been described in detailherein, those skilled in the art will readily appreciate that manymodifications are possible in the exemplary embodiments withoutmaterially departing from the novel teachings and advantages of theembodiments of the present disclosure. Accordingly, all suchmodifications are intended to be included within the scope of theembodiments of the present disclosure as defined in the followingclaims. In the claims, means-plus-function clauses are intended to coverthe structures described herein as performing the recited function andnot only structural equivalents, but also equivalent structures.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover any andall such modifications, enhancements, and other embodiments that fallwithin the scope of the present invention. Thus, to the maximum extentallowed by law, the scope of the present invention is to be determinedby the broadest permissible interpretation of the following claims andtheir equivalents, and shall not be restricted or limited by theforegoing detailed description.

What is claimed is:
 1. An information handling system, comprising: aplurality of peripheral component interconnect express (PCIe) devices;and a basic input/output system (BIOS) to: receive a system managementinterrupt (SMI) in response to a detection of an error on a first PCIedevice of the PCIe devices; collect data associated with the first PCIedevice, wherein the data includes a friendly full device description forthe first PCIe device; based on the friendly full device description,determine a friendly name for the PCIe device; and provide an errormessage on a display device of the information handling system, whereinthe error message includes a type of the error detected and the friendlyname for the PCIe device.
 2. The information handling system of claim 1,wherein the determination of the friendly name, the BIOS further tocorrelate the friendly full device description for the PCIe device withthe friendly name for the PCIe device in a look-up table.
 3. Theinformation handling system of claim 2, further comprising a memory tocommunicate with the BIOS, the memory to store the look-up table.
 4. Theinformation handling system of claim 3, during boot operations of theinformation handling system, the BIOS further to: perform an PCIeenumeration process to collect information for all of the PCIe devices;and generate the look-up table based on the information for all of thePCIe devices.
 5. The information handling system of claim 4, wherein thelook-up table includes a different entry for each of the PCIe devices inthe information handling system.
 6. The information handling system ofclaim 4, wherein the BIOS further to provide the look-up table to asystem management mode (SMM) reliability, availability, andserviceability (RAS) driver.
 7. The information handling system of claim1, wherein the providing of the look-up table, the BIOS further toprovide the SMM RAS driver with a pointer identifying a location in thememory associated with the look-up table.
 8. The information handlingsystem of claim 1, wherein the friendly name is an alphanumeric string.9. A method, comprising: detecting an error on a peripheral componentinterconnect express (PCIe) device; in response to the detection of theerror, providing a system management interrupt (SMI) to a basicinput/output system (BIOS) of the information handling system;collecting, by the BIOS, data associated with the PCIe device, whereinthe data includes a friendly full device description for the PCIedevice; determining, based on the friendly full device description andby the BIOS, a friendly name for the PCIe device; and providing an errormessage on a display device of the information handling system, whereinthe error message includes a type of the error detected and the friendlyname for the PCIe device.
 10. The method of claim 9, further comprisingcorrelating the friendly full device description for the PCIe devicewith the friendly name for the PCIe device in a look-up table.
 11. Themethod of claim 10, wherein during boot operations of the informationhandling system, the method further comprises: performing an PCIeenumeration process to collect information for all of the PCIe devices;and generating the look-up table based on the information for all of thePCIe devices.
 12. The method of claim 11, wherein the look-up tableincludes a different entry for each of the PCIe devices.
 13. The methodof claim 11, further comprising providing the look-up table to a systemmanagement mode (SMM) reliability, availability, and serviceability(RAS) driver.
 14. The method of claim 13, wherein the providing of thelook-up table, the method further comprising providing the SMM RASdriver with a pointer identifying a location in the memory associatedwith the look-up table.
 15. The method of claim 9, wherein the friendlyname is an alphanumeric string.
 16. An information handling system,comprising: a plurality of peripheral component interconnect express(PCIe) devices; a memory to store a look-up table associated with thePCIe devices; and a basic input/output system (BIOS) to communicate withthe memory, wherein during boot operations of the information handlingsystem, the BIOS: performs a PCIe enumeration process to collectinformation for all of the PCIe devices; and generates the look-up tablebased on the information for all of the PCIe devices, wherein thelook-up table includes a friendly full device description for a firstone of the PCIe devices and a friendly name for the first PCIe device,wherein the friendly name is an alphanumeric string; wherein during aruntime of the information handling system, the BIOS to: receive aplurality of system management interrupts (SMIs), wherein the at leastone of the SMIs is in response to a detection of an error on a firstPCIe device of the PCIe devices; collect data associated with the firstPCIe device, wherein the data includes the friendly full devicedescription for the first PCIe device; based on the friendly full devicedescription and the look-up table, determine a friendly name for thePCIe device; and provide an error message on a display device of theinformation handling system, wherein the error message includes a typeof the error detected and the friendly name for the PCIe device.
 17. Theinformation handling system of claim 16, wherein during the runtime ofthe information handling system, the BIOS further to correlate thefriendly full device description for the PCIe device with the friendlyname for the PCIe device in a look-up table.
 18. The informationhandling system of claim 16, wherein the look-up table includes adifferent entry for each of the PCIe devices.
 19. The informationhandling system of claim 16, wherein during the boot operations, theBIOS further to provide the look-up table to a system management mode(SMM) reliability, availability, and serviceability (RAS) driver. 20.The information handling system of claim 19, wherein the providing ofthe look-up table, the BIOS further to provide the SMM RAS driver with apointer identifying a location in the memory associated with the look-uptable.